1. Field of the Invention
The present invention relates to a signal compensation circuit and a demodulating circuit that are useful in, for example, a mobile communications receiver.
2. Description of the Related Art
When a signal modulated by frequency-shift keying (FSK, a common modulation method in wireless communications) is demodulated, the direct-current (DC) component of the demodulated signal (also referred to as the detected signal) may include an undesired and variable offset due to, for example, a difference between the signal frequency and the predetermined carrier frequency.
U.S. Pat. No. 6,104,238 (hereinafter, Document D1) discloses a method of reducing DC potential variations in the detected output signal by varying the center frequency of, for example, a channel selection filter in a stage preceding the detector. In this method, variations in the DC offset are tracked by smoothing the detected signal and adding its DC component to the frequency control signal supplied to the filter.
U.S. Pat. No. 5,412,692 (hereinafter, Document D2) discloses a method of obtaining a final output signal by detecting the maximum and minimum levels of the detected output signal, generating a potential intermediate between them, and using the intermediate potential as a reference potential for a comparator circuit. The intermediate potential tracks DC offset variations in the detected output signal.
In some types of wireless communication systems, the data transmitting state alternates with the data receiving state; the two states may follow one another continuously, or there may be a rest interval between them (an interval in which data are neither transmitted nor received, although the power supply voltage is applied). Therefore, when the communication system switches into the data receiving state, the received signal reaches the receiver in a burst and the DC level of the detected signal changes dynamically.
In wireless communication systems, a preamble pattern, which is added to the head of the transmitted signal, is generally used to enable compensation for this dynamic DC offset. The pattern length, however, differs from one wireless communication system to another, and it is necessary to track the dynamic DC offset at high speed in order to demodulate a signal with an extremely short pattern length (a length of four bits, for example).
Moreover, the transmitted signal may include intervals in which the same code level (high level or low level) occurs successively; the demodulating circuit is required to operate without error over such runs of identical codes up to a run length specified for the application system. Generally speaking, the capability to tolerate long run lengths conflicts with the capability for high-speed DC offset compensation.
The circuit configuration described in Document D1 is problematic in that the time needed for DC offset compensation is the total sum of the time needed for smoothing the detected signal and the absolute delay times of the channel selection filter and detector, and in that high-speed DC offset compensation is difficult if a high-order filter is used in the demodulating circuit.
The circuit configuration described in Document D2 is also problematic, in that high-speed DC offset compensation requires the time constants of the integrating circuits that detect the maximum and minimum levels of the detected signal to be decreased, which reduces the run-length tolerance.
There is a need for a demodulating circuit that can execute rapid DC offset compensation and at the same time can tolerate DC offset variations caused by runs of identical codes, as well as a need for a signal compensation circuit that is suitable to be applied in such a demodulating circuit.